Several patents and publications identified in the "Background Art" section hereof further disclose Level Sensitive Scan Design (LSSD) methods and discipline that address the afore-recited needs. With the exception of a limited number of patents directed to packaging all the patents come under the generic title LSSD or are closely related thereto. A common thrust of the LSSD discipline is to prescribe a built-in capability for every LSI unit, such as chip module etc., whereby the entire logic state of the unit, under test, can be explicitly set and/or examined through exercising certain input/-output (I/O) procedures at a limited number of I/O terminals. This requirement is implementable by imparting a shift register capability to every one of the logic system latches in the unit and thereupon organizing these shift register latches (SRL's) into one or more shift register data channels with their terminal stages accessible to the outside world. Further information and details of operation using the SRL facility of LSSD are given in a number of prior art patents and publications fully identified in the "Background Art" section set forth hereinafter. [Reference may be made to the following U.S. Pat. Nos. 3,784,254 entitled "Level Sensitive Logic System" granted Jan. 1, 1974 to E. B. Eichelberger; 3,761,695 entitled "Method of Level Sensitive Testing A Functional Logic System" granted Sept. 25, 1973 to E. B. Eichelberger; and 3,784,907 entitled "Method of Propagation Delay Testing A Functional Logic System" granted Jan. 8, 1974 to E. B. Eichelberger]. Stated very briefly, the LSSD approach comprises a test operation wherein certain desired logic test patterns are serially inputted and shifted to the appropriate latch locations when the unit is operated in the "shift mode" (i.e., by withholding the system clock excitations and turning on the shifting clock to the unit). When this is done, the latch states will provide the desired stimuli for the testing of the related logic nets. Now, propagate the test patterns through the nets by executing one or more steps of the "Function Mode" operation (i.e., by exercising one or more system clock excitations). The response pattern of the logic networks to the applied stimuli is now captured by the system latches, in a known manner depending on certain details of hardware design, often replacing the original inputted test patterns. Then, the system reverts to the shift-mode operation, outputting the response patterns for examination and comparison with standard patterns which should be present if the circuitry has operated properly.
In accordance with the prior art teaching, the testing of each chip contained in a high circuit density packaging structure (without disconnecting the chip to be tested from the high circuit density packaging structure, i.e., interconnecting circuitry and other chips) required an array of precisely positioned exposed contact pads for each chip contained and interconnected in the high circuit density packaging structure. The array of precisely positioned exposed contact pads for each chip was utilized by a mechanical test probe head in the testing of the chip subsequent to interconnection of the chip in the high circuit density packaging structure. The array of precisely positioned exposed contact pads (also termed "Engineering Change Pads") for each chip and interconnected in the packaging structure, as known in the art, are also available for engineering change purposes.
This method of testing has the disadvantage of requiring the alignment and subsequent stepping of the probe over the surface of the package--a time consuming process. Since the probe head contacts one chip site at a time, the connections between the chips on the package are not tested.
U.S. Pat. No. 4,220,917 discloses a plurality of interconnected integrated circuit chips each having an array of engineering pads for contact by a test probe and also for engineering change purposes. (U.S. Pat. No. 4,220,917 entitled "Test Circuitry For Module Interconnection Network" granted Sept. 2, 1980 to M. T. McMahon, Jr., and of common assignee herewith).
In accordance with the prior art teaching, an alternate approach to testing circuitry on a high density packaging structure requires through the package-pins test. The LSSD technique is employed to design the component chips of the package as well as to design the inter-chip connections on the package. Automatic test generation for dense LSSD logic structures employs the partitioning technique described in "Test Generation For Large Logic Networks" by P. S. Bottoroff, R. E. France, N. H. Garges and E. J. Orosz, 14th Design Automation Conference Proceedings, June 20, 21 and 22, 1977, New Orleans, La., IEEE Catalog Number 77, CH 1216-1C, pages 479 to 485. The technique logically partitions the dense LSSD logic into portions which are bounded on the inputs and outputs by SRL's and package pins. Tests are then generated individually for each partition and subsequently applied through the pins of the package at the tester. The limitations of the partitioning at the tester. The limitations of the partitioning technique are (a) the partition size can exceed the capacity of available LSSD test generators, (b) the turnaround time to generate package tests is excessive, and (c) the turnaround time to re-generate package tests due to an engineering change is also excessive.
The present invention provides for a design approach and testing method which circumvents the afore-recited problems and will allow testing of each individual chip of a plurality of interconnected chips without physically disconnecting the chip under test and without the need for and utilization of test equipment having a precision probe head and a high precision step and repeat mechanism.
As will be fully apparent from the hereinafter set-forth detailed description of our invention, the practice of our invention is not limited to any particular physical packaging structure. Merely by way of example, the high circuit density packaging structure containing a plurality of interconnected semiconductor chips may be generally of the type disclosed in one or more of the following patents: U.S. Pat. No. 4,245,273 entitled "Package For Mounting and Interconnecting A Plurality of Large Scale Integrated Semiconductor Devices" granted Jan. 13, 1981 to I. Feinberg and of common assignee herewith; U.S. Pat. No. 3,564,114 entitled "Universal Multilayer Printed Circuit Board" granted Feb. 16, 1971 to M. Blender et al; U.S. Pat. No. 4,263,965 entitled "Leaved Thermal Cooling Module" granted Apr. 28, 1981 to M. S. Mansuria et al. and of common assignee herewith, Ser. No. 133,898, filed Jan. 21, 1980; U.S. Pat. No. 4,138,692 entitled "Gas Encapsulated Cooling Module" granted Feb. 6, 1979 to Robert G. Meeker et al., and of common assignee herewith; U.S. Pat. No. 4,233,645 entitled "Semiconductor Package with Improved Conduction Cooling Structure" granted Nov. 11, 1980 to D. Balderes et al., and of common assignee herewith; U.S. Pat. No. 3,993,123 entitled "Gas Encapsulated Cooling Module" granted Nov. 23, 1976 to R. C. Chu et al., and of common assignee herewith; U.S. Pat. No. 3,726,002 entitled "Process For Forming A Multilayer Glass-Metal Module Adaptable For Integral Mounting to Dissimilar Refractory Substrate: granted Apr. 10, 1973 to B. Greenstein et al., and of common assignee herewith; U.S. Pat. No. 3,838,204 entitled "Multilayer Circuits" granted Sept. 24, 1974 to J. Ahn et al., and of common assignee herewith; U.S. Pat. No. 3,999,004 entitled "Multilayer Ceramic Substrate" granted Dec. 21, 1976 to O. J. Chirino et al., and of common assignee herewith; U.S. Pat. No. 3,851,221 entitled "Integrated Circuit Package" granted Nov. 26, 1974 to P. E. Beaulieu and of common assignee herewith; and U.S. patent application Ser. No. 008,375 entitled "Improved Heat Transfer Structure For Integrated Circuit Package" filed Feb. 1, 1979 by E. Berndlmaier et al., and of common assignee herewith, granted as U.S. Pat. No. 4,323,914 on Apr. 6, 1982.